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課程概述 |
一. Course Outline:
- HDL grammar, coding guideline, and synthesis guideline (8 weeks)
- MIPS CPU design and implementation (6 weeks)
- Final presentation, discussion, and demo (3 weeks)
二. 教科書:
- (Main) “Advanced Digital Design with the Verilog HDL,” by M. D. Ciletti, Prentice Hall, 2003.
- “Verilog HDL: A Guide to Digital Design and Synthesis,” 2nd ed., by Samir Palnitkar, SunSoft, 2003 (全華代理)
- “Verilog Styles for Synthesis of Digital Systems,” by David R. Smith and Paul D. Franzon, Prentice Hall, 2000 (全華代理)
- “Computer organization and design: The hardware/software interface,” by David A. Patterson and John L. Hennessy, 2005, 3rd Edition (新月, 東華).
- “Reuse Methodology Manual for System-On-A-Chip Designs,” 3rd Edition, by Michael Keating, Pierre Bricaud, Kluwer Academic Publishers, 2002.
三. 成績評量方式
1. Participation 2% (about four times).
2. One mid-terms 24%
3. Final Projects (demo and presentation) 36%
4. Computer Labs and Homework (about four labs and four homework) 38%
四. 預修課程
- Programming Language, Logic Design (basic)
- Computer Organization and Design (required), VLSI Design (optional)
五. URL: http://access.ee.ntu.edu.tw
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課程目標 |
Digital system design plays an important role in implementing digital functions in modern system-on-chip (SOC) designs. In this course, we will focus on developing the design skills for undergraduate students so that they can be familiar with state-of-the-art digital front-end design skills and flow. This course covers 3 parts:
- Firstly, we will introduce the Hardware Description Language (HDL). The chosen HDL is Verilog. We will formally cover the HDL grammar, coding guideline, synthesis guideline, which conforms to modern cell-based synthesis flow and Reuse Manual Methodology (RMM).
- Secondly, we will ask students to design an advanced MIPS CPU. It is based on the knowledge of “Computer Organization and Design. The assignment covers (a) Instruction development, (b) HDL coding and simulation of major blocks such as Arithmetic Logic Unit (ALU) and Control Unit (CU), (c) Enhanced CPU design with Pipelining and Forwarding, (d) Integration of whole design.
- Thirdly, port the MIPS CPU design to FPGA board and perform emulation (optional). |